With the increase in concern for safety and crime prevention in recent years, cameras are being installed in various locations for the purpose of safety and crime prevention. Such functions as automobile accident avoidance and the management of office check-in and check-out are beginning to be realized by subjecting pictures taken by such cameras for safety and crime prevention to picture processing. This picture processing requires a large volume of computation in a short time period. As a result, parallel processors that are capable of processing a multiplicity of data at high speed are being used in the equipment that carries out the picture processing. Parallel processors are processors that can handle a plurality of items of data by a single operation command.
As one such parallel processor, SIMD (Single Instruction Multiple Data) array processors are being developed in which a multiplicity of processing elements operate in parallel and operate based on a single operation command. Processing elements are hereinbelow abbreviated as “PE.” In these SIMD-array processors, the parallel operation of a multiplicity of PEs enables the realization of processing that features both high performance and low power consumption.
Algorithms exist for collecting data that satisfy predetermined conditions from PEs that, as a result of carrying out processing, have these data that satisfy the predetermined conditions as processing results. For example, in a pattern-matching process, each PE carries out matching of different pictures in parallel, and only data of PEs that achieved matching are collected. The determination of whether a PE has data that satisfy the predetermined condition is realized by condition flags of the PEs. The condition flags are, for example, flags represented by one bit and, depending on the data belonging to the PEs, indicate “1” when the data satisfy the predetermined condition and indicate “0” when the data do not satisfy the predetermined conditions. In the following explanation, the setting of the bit to “1” will be referred to as “active,” and a setting of the bit to “0” will be referred to as “inactive.”
In an SIMD-array processor, data and condition flags are collected from all PEs, and determination of whether to use the collected data as collection result data is realized by sequentially judging the collected condition flags.
However, in a method of this type, data that do not satisfy the predetermined condition must also be collected and condition flags must be sequentially judged for each PE. As a result, the number of clock cycles for collecting data that satisfy the predetermined condition becomes voluminous.
In response, Patent Document 1 discloses an SIMD-array processor that collects only data that satisfy a predetermined condition in order from PEs for which a PE number that is given to each PE is large or from PEs for which the PE number is small.
FIG. 1 shows an example of the configuration of an SIMD-array processor that collects only data that satisfy a predetermined condition in order from PEs for which the PE number is small or from PEs for which the PE number is large.
The SIMD-array processor shown in FIG. 1 is equipped with PEs 300-1-300-n and central processor 400.
Each of PEs 300-1-300-n is equipped with general register 301 that processes commands supplied from central processor 400, ALU (Arithmetic and Logic Unit) group 302, F-register 303 that stores condition flags, and comparator 304. The ALU is a circuit that carries out arithmetic processing such as the four basic operations of arithmetic or logical operations.
Comparator 304 compares the PE number supplied from register 404 of central processor 400 and its own PE number.
Central processor 400 supplies commands to PEs 300-1-300-n and controls the overall SIMD-array processor. Central processor 400 is equipped with general register 401 that processes commands, ALU group 402, priority encoder 403, and registers 404 and 405.
Priority encoder 403 checks the condition flags of PEs 300-1-300-n based on the predetermined order of priority, selects PE numbers one at a time that indicate PEs for which the condition flags are active, and stores the selected PE numbers in register 404.
Register 404 stores the PE numbers that are selected by priority encoder 403, and then supplies the stored PE numbers to PEs 300-1-300-n. 
Register 405 stores the data that are supplied from PEs 300-1-300-n. 
In the SIMD-array processor that is disclosed in the above-described Patent Document 1, data that satisfy a predetermined condition are collected by the procedures shown in (1)-(7) below.
(1) Condition flags that are stored in F-registers 303 of PEs 300-1-300-n are applied as input to priority encoder 403 of central processor 400.
(2) Priority encoder 403 selects one condition flag that is active from the condition flags of PEs 300-1-300-n based on a predetermined order of priority.
(3) The PE number of PEs 300-1-300-n that corresponds to the selected condition flag is stored in register 404.
(4) Using PE designation path 350, the PE number that was stored in (3) above is broadcast to all PEs 300-1-300-n. 
(5) In each of PEs 300-1-300-n, the PE number that was broadcast is compared with the PE number of that PE 300-1-300-n. 
(6) The condition flag of only that PE in which the PE number that was broadcast matched its own PE number is updated to be inactive. This PE then supplies the data of general register 301 to register 405 by way of data collection path 450.
(7) The data that were supplied from the PE by way of data collection path 450 are stored in register 405.